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1 copyright ? cirrus logic, inc. 2004 (all rights reserved) cirrus logic, inc. http://www.cirrus.com CS3001 cs3002 precision low voltage amplifier; dc to 2 khz features low offset: 10 v max low drift: 0.05 v/c max low noise ?6 nv/ hz @ 0.5 hz ? 0.1 to 10 hz = 125 nvp-p ? 1/f corner @ 0.08 hz open-loop voltage gain ? 300 db typical ? 200 db minimum rail-to-rail output swing slew rate: 5 v/ s applications thermocouple/thermo pile amplifiers load cell and bridge transducer amplifiers precision instrumentation battery-powered systems description the CS3001 single amplifier and the cs3002 dual am- plifier are designed for precision amplification of low level signals and are ideally suited to applications that require very high closed loop gains. these amplifiers achieve excellent offset stab ility, super high open loop gain, and low noise over time and temperature. the de- vices also exhibit excellent cmrr and psrr. the common mode input range includes the negative supply rail. the amplifiers operate with any total supply voltage from 2.7 v to 6.7 v (1.35 v to 3.35 v). pin configurations pwdn -in +in v- nc v+ output nc 1 2 3 4 8 7 6 5 - + CS3001 8-lead soic out a -in a +in a v- v+ out b -in b +in b 1 2 3 4 8 7 6 5 a b - - + + cs3002 8-lead soic noise vs. frequency (measured) 1 10 100 0.001 0.01 0.1 1 10 frequency (hz) nv / hz CS3001 r1 100 r2 64.9k c1 0.015 f dexter research thermopile 1m thermopile amplifier with a gain of 650 v/v oct ?04 ds490f3
CS3001 cs3002 2 table of contents 1. characteristics and specifications ............................................................3 1.1 electrical characteristics .................... ..................................................................3 1.2 absolute maximum rating s ..................................................................................4 2. performance plots .............................................................................................4 3. CS3001/cs3002 overview .......................................................................................7 3.1 open loop gain and phase response ................................................................7 3.2 open loop gain and stability compensation ......................................................8 3.3 powerdown (pdwn) ..........................................................................................10 3.4 applications ........................................................................................................10 4. package drawing ...............................................................................................13 5. ordering information ......................................................................................14 list of figures figure 1. noise vs frequency (measured) .........................................................................4 figure 2. 0.01 hz to 10 hz noise .......................................................................................4 figure 3. noise vs frequency ............................................................................................4 figure 4. offset voltage stability (dc to 3.2 hz) ...............................................................4 figure 5. open loop gain and phase vs frequency .........................................................5 figure 6. open loop gain and phase vs freq uency (expanded) .....................................5 figure 7. input bias current vs supply voltage (cs3002) .................................................6 figure 8. input bias current vs common mode voltage ...................................................6 figure 9. CS3001/cs3002 open loop gain and phase response ..................................7 figure 10. non-inverting gain configuration .....................................................................8 figure 11. non-inverting gain configuration with compensation ......................................9 figure 12. loop gain plot: un ity gain and with pole-zero co mpensation ......................10 figure 13. thermopile amplifier with a gain of 650 v/v ..................................................11 figure 14. load cell bridge am plifier and a/d converter ...............................................12 contacting cirrus logic support for all product questions and in quiries contact a cirrus logic sales representative. to find one nearest you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of li ability. no responsibility is assumed by cirrus for the use of this inform ation, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for ge neral distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potentia l risks of death, personal injury, or severe prop- erty or environmental da mage (?critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military appl ications, products surgically implanted into the body, li fe support products or other critical applications (including medical devices, aircraft systems or components an d personal or automo tive safety or se- curity devices). inclusion of ci rrus products in such application s is understood to be fully at the customer's risk and cir- rus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is us ed in such a manner. if the customer or customer's customer uses or per mits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, director s, employees, di stributors and other ag ents from any and al l liability, includ- ing attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.
CS3001 cs3002 3 1. characteristics and specifications 1.1 electrical characteristics v+ = +5 v, v- = 0v, vcm = 2.5 v ( note 1 ) notes: 1. symbol ? ? ? denotes specification ap plies over -40 to +85 c. 2. this parameter is guaranteed by design and labora tory characterization. thermocouple effects prohibit accurate measurement of these parameters in automatic test systems. 3. 1000-hour life test data @ 125 c indicates rando mly distributed variation approximately equal to measurement repeat ability of 1 v. 4. measured within the specified common mode range limits. 5. guaranteed within the output limits of (v+ -0.3 v) to (v- +0.3 v). tested with proprietary production test method. 6. pwdn input has an internal pullup resistor to v+ of approximately 800 k ? and is the major source of current consumption when pwdn is active low. 7. the device has a controlled start-up behavior due to its complex open loop gain characteristics. start- up time applies when supply voltage is applied or when pdwn is released. parameter CS3001/cs3002 unit min typ max input offset voltage ( note 2 ) ? --10 v average input offset drift ( note 2 ) ? - 0.01 0.05 v/oc long term input offset voltage stability ( note 3 ) input bias current t a = 25o c ? - - 100 - - 1000 pa pa input offset current t a = 25o c ? - - 200 - - 2000 pa pa input noise voltage density r s = 100 ? , f 0 = 1 hz r s = 100 ? , f 0 = 1 khz - - 6 6 input noise voltage 0.1 to 10 hz - 125 nv p-p input noise current density f 0 = 1 hz - 100 input noise current 0.1 to 10 hz - 1.9 pa p-p input common mode voltage range ? -0.1 - (v+)-1.25 v common mode rejection ratio (dc) ( note 4 ) ? 115 120 - db power supply rejection ratio ? 120 136 - db large signal voltage gain r l = 2 k ? to v+/2 ( note 5 ) ? 200 300 - db output voltage swing r l = 2 k ? to v+/2 r l = 100 k ? to v+/2 ? +4.7 - +4.99 -v v slew rate r l = 2 k, 100 pf 5 - v/s overload recovery time - 100 - s supply current CS3001 cs3002 pwdn active (CS3001 only) ( note 6 ) ? ? ? - - 2.1 3.6 2.8 4.8 15 ma ma a pwdn threshold ( note 6 ) ? (v+) -1.0 - - v start-up time ( note 7 ) ? -912 ms nv/ hz nv/ hz fa/ hz
CS3001 cs3002 4 1.2 absolute maximum ratings 2. performance plots parameter min typ max unit supply voltage [(v+) - (v-)] 6.8 v input voltage v- -0.3 v+ +0.3 v storage temperature range -65 +150 oc noise vs. frequency (measured) 1 10 100 0.001 0.01 0.1 1 10 frequency (hz) nv / hz figure 1. noise vs frequency (measured) - 1 0 0 - 5 0 0 5 0 1 0 0 tim e (se c) n v 0 1 2 34 5 6 78 9 10 figure 2. 0.01 hz to 10 hz noise 1 10 100 1000 10 100 1k 10k 100k 1m 10m frequency (hz) nv / hz figure 3. noise vs frequency time (1 hour) -100 -75 -50 -25 0 25 50 75 100 nv = 13 nv figure 4. offset voltag e stability (dc to 3.2 hz)
CS3001 cs3002 5 performance plots (cont.) figure 5. open loop gain and phase vs frequency 100 k -500 -400 -300 -200 -100 0 100 200 300 400 500 1 10 100 1000 10000 100000 100000 0 1e+07 frequency (hz) gain (db) phase (degrees) 1 10 100 1 k 10 k 1 m 10 m frequency (hz) gain phase -360 -315 -270 -225 -180 -135 -90 -45 10k 100k 1m 10 m gain (db) phase (degrees) 0 20 40 60 80 100 figure 6. open loop gain an d phase vs frequency (expanded)
CS3001 cs3002 6 performance plots (cont.) supp ly voltage (v) input bias current (pa) a1- a1+ b1- a2+ b1+ a2- b2- b2+ 1.35 2 2.5 3.35 -200 -150 -150 -100 -100 0 -50 -50 cm = 0 v figure 7. input bias current vs supply voltage (cs3002) -3 -2 -1 0 1 2 3 012345 common mode voltage (vs = 5v) bias current normalized to cm = 2.5 v figure 8. input bias curren t vs common mode voltage
CS3001 cs3002 7 3. CS3001/cs3002 overview the CS3001/cs3002 amplifie rs are designed for precision measurement of signals from dc to 2 khz when operating fr om a supply voltage of +2.7 v to +6.7 v ( 1.35 to 3.35 v). the ampli- fiers are designed with a patented architecture that utilizes multiple amplifier stages to yield very high open loop gain at frequenc ies of 10 khz and below. the amplifiers yield low noi se and low offset drift while consuming relativel y low supply current. an increase in noise floor a bove 2 khz is the result of intermediate stages of the amplifier being operated at very low currents. th e amplifiers are intended for amplifying small signals with large gains in ap- plications where the output of the amplifier can be band-limited to frequencies below 2 khz. 3.1 open loop gain and phase response figure 9 illustrates the open loop gain and phase re- sponse of the CS3001/cs3002. the gain slope of the amplifier is about ?100 db/decade between 500 hz and 60 khz and tr ansitions to ?20 db/de- cade between 60 khz and its unity gain crossover frequency at about 4.8 mhz. phase margin at unity gain is about 70 degrees ; gain margin is about 20 db. -360 -315 -270 -225 -180 -135 -90 -45 10k 100k 1m 10m gain (db) phase (degrees) 0 20 40 60 80 100 -100 db/ dec -20 db/ dec figure 9. CS3001/cs 3002 open loop gain and phase response
CS3001 cs3002 8 3.2 open loop gain and st ability compensation the CS3001 and cs3002 ac hieve ultra-high open loop gain. figure 10 illustrates the amplifier in a non-inverting gain confi guration. the open loop gain and phase plots indica te that the amplifier is stable for closed-loop gains less than 50 v/v. for a gain of 50, the phase margin is between 40 and 60 depending upon the loading conditions. as shown in figure 11, on page 9 , the operational amplifier has an input capacitance at the + and ? signal inputs of typically 50 pf. this capacitance adds an addi- tional pole in the loop gain transfer function at a frequency of f = 1/(2 r*c in ) where r is the paral- lel combination of r1 and r2 ( r1 || r2 ). a higher value for r produces a pol e at a lower frequency, thus reducing the phase ma rgin. r1 is recommend- ed to be less than or e qual to 100 ohms, which re- sults in a pole at 30 mhz or higher. if a higher value of r1 is desired, a compensation capacitor (c2) should be added in parallel with r2. c2 should be chosen such that r2*c2 r1*c in . r1 r2 vin vo r s figure 10. non-inverting gain configuration
CS3001 cs3002 9 the feedback capacitor c2 is required for closed- loop gains greater than 50 v/v. the capacitor in- troduces a pole and a zero in the loop gain transfer function, this indicates that the separation of the pole and the zero is governed by the closed loop gain. it is required that the zero falls on the steep slope (?100 db/decade) of the loop ga in plot so that there is some gain higher than 0 db (typically 20 db) at the hand-over frequency (t he frequency at which the slope changes from ? 100 db/decade to ?20 db/decade). 50 pf 50 pf r1 r2 vin vo c2 c in c in choose c2 so that r2c2 r1c in figure 11. non-inverting gain configuration with compensation t 1 s z 1 ---- - + ?? ?? ? 1 s p 1 ----- + ?? ?? ----------------------- a ol = p 1 1 2 r 1 r 2 || () c 2 ------------------------------------ - 1 2 r 1 c 2 () ------------------------ - ? = for r 2 r 1 ? z 1 1 2 ar 1 () c 2 ----------------------------------- = where a r 2 r 1 ------ =
CS3001 cs3002 10 the loop gain plot shown in figure 12 illustrates the unity gain configurat ion, and indicates how this is modified when using the amplifier in a higher gain configuration with co mpensation. if it is con- figured for higher gain, for example, 60 db, the x?axis will move up by 60 db (line b). capacitor c2 adds a zero and a pole. the modified plot indi- cates the effects of intr oducing the pole and zero due to capacitor c2. the pol e can be located at any frequency higher than th e hand-over frequency, the zero has to be at a frequency lower than the hand- over frequency so as to pr ovide adequate gain mar- gin. the separation between the pole and the zero is governed by the closed loop gain. the zero (z 1 ) occurs at the intersecti on of the ?100 db/decade and ?80 db/decade slopes. the point x in the fig- ure should be at closed loop gain plus 20 db gain margin. the value for c2 = 1/(2 r1p1). using p1 = 1 mhz works very we ll and is independent of gain. as the closed loop gain is changed, the zero location is also modified if r1 remains fixed. capacitor c2 can be increased in value to limit the amplifier?s rising noise above 2 khz. 3.3 powerdown ( pdwn ) the CS3001 single amplif ier provides a power- down function on pin 1. if th is pin is left open the amplifier will operate normally. if the powerdown is asserted low, the amplifier will go into a low power state. there is a pull-up resistor (approxi- mately 800 k ohm) inside the amplifier from pin 1 to the v+ supply. the curr ent through this pull-up resistor is the main sour ce of current drain in the powerdown state. 3.4 applications the CS3001 and cs3002 amplifiers are optimum for applications th at require high gain and low drift. figure 13 illustrates a thermopile amplifier with a gain of 650 v/v. the thermopile outputs only a few millivolts when subjected to infrared radiation. the amplifier is compensated and bandlimited by c1 in combination with r2. -100 db/dec |t| (log gain) -80 db/dec z 1 p 1 margin -20 db/dec 50khz 1mhz 5mhz desired closed loop gain x frequency b figure 12. loop gain plot: unity ga in and with pole-zero compensation
CS3001 cs3002 11 figure 14, on page 12 illustrates a load cell bridge amplifier with a gain of 768 v/v. the load cell is excited with +5 v and has a 1 mv/v sensitivity. its full scale output signal is amplified to produce a fully differential 3.8 v into the cs5510/12 a/d converter. this circuit operates from +5 v. a similar circuit operating from +3 v can be constructed using the cs5540/cs5541 a/d con- verters. CS3001 r1 100 r2 64.9k c1 0.015 f dexter research thermopile 1m thermopile amplifier with a gain of 650 v/v figure 13. thermopile amplifi er with a gain of 650 v/v
CS3001 cs3002 12 +5 v va 1 m v/v - + 350 ? + - - + x768 140 k ? ? ? ? ? cs5510/12 +5 v +5 v counter/tim er s c lk = 1 0 kh z to 10 0 (32.768 ) sclk = 10 khz to 100 khz (32.768 nom inal ) figure 14. load cell bridge amplifier and a/d converter
CS3001 cs3002 13 4. package drawing inches millimeters dim min max min max a 0.053 0.069 1.35 1.75 a1 0.004 0.010 0.10 0.25 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.19 0.25 d 0.189 0.197 4.80 5.00 e 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 h 0.228 0.244 5.80 6.20 l 0.016 0.050 0.40 1.27 0 8 0 8 jedec #: ms-012 8l soic (150 mil body) package drawing d h e e b a1 a c l seating plane 1
CS3001 cs3002 14 5. ordering information part # temperature range package description CS3001-isz -40 c to +85 c 8-lead soic, lead free cs3002-isz -40 c to +85 c 8-lead soic, lead free note: add the letter r to the part # to order reels. there are 2000 pieces per reel.

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